Dipartimento di Automatica e Informatica, 3rd floor, zone 3C (directions)
Politecnico di Torino
Corso Duca degli Abruzzi, 24
10129 Torino - Italia
How to reach me
Tel.: +39 011 090.7008
Fax: +39 011 090.7099
Mobile: +39 338 6604746 (only urgent matters, please)
Home: +39 0175 87562 (only urgent matters, please)
E-mail: fulvio.risso[at]polito.it (institutional) fulvio[at]frisso.net (personal)
Office hours and appointments for students
I do not schedule fixed office hours. If you need an appointment, please check my calendar and follow the suggestions on that page.
I'm currently involved in investigating high-speed packet processing (i.e., 10Gbps and beyond), while maintaining flexibility. We designed
several components that can be used to achieve this vision, from the
highly successful NetPDL language, the NetVM virtual machine, and their integration in the NetBee library. I also tried to apply these technologies to the problem of Traffic Classification, hence I spent some time on that topic too. With some very smart PhD student we had a look at the word of network processors and multicore/graphical CPU for networking; the first result is the iNFAnt pattern matching engine on nVidia graphics cards.
Currently I'm exploring the world of network processing, a.k.a. how to make the network programmable. This concept is usually referred as "Software Defined Networks", although it is so vague that you can do almost everything under that umbrella. I prefer to focus on a an idea that an be defined as User Programmable Networks, which evolved in a research project called FROG (Flexible and pROGrammable network device).
My past research activities included Quality of Service in Packet Switched Networks, Scheduling Algorithms (particularly Class Based Queuing), Scheduling, Voice over IP, management of resources in peer-to-peer networks.
Some more pointers
This is a list of drafts I am currently working on. I hope to see these documents to become papers soon.
Here there is the list of papers that got published somewhere recently.
- User-oriented Network Functions Virtualization (Silicon Valley tour, March 2014)
- Revealing the FROG (Telecom Italia, December 2013)
- Research Directions in Network Service Chaining (SDN4FNS, November 2013)
- Some Controversial Opinions on Software-Defined Data Plane Services (SDN4FNS, November 2013)
- Software Defined Networks and Beyond (Narus, October 2013)
- Customizing Data Plane Processing in Edge Router (Silicon Valley tour, February 2013)
- Filtering Network Traffic Based on Protocol Encapsulation Rules (ICNC 2013, January 2013)
- Customizing Data Plane Processing in Edge Routers (1st European Workshop on Software Defined Networks, October 2012)
- Software Defined Networks and Beyond (Telecom Italia, April 2012)
- Applications Like Bees (Polaris Future Cities Workshop, Porto, October 2011)
- Will low-power CPUs replace network processors in future network devices? (Cisco Systems, Nvidia, Telecom Italia, June 2011)
- A possible future for network processors (Institute Eurecom, Nice, April 2011)
- Pattern matching on GPU devices (Telecom Italia, Torino, December 2010)
Some tools I'm currently involved in
- Dyn@NG: a simple interface for virtualizing Cisco labs (throgh Dynamips)
- NetBee: the evolution of the WinPcap
library; it offers a much more powerful object-based interface and it
implements several modules (packet decoding, packet sniffing, ...) that
can be used from external programs. Available for Windows and Linux.
Some tools I was involved in
- WinPcap: a library for packet capture and network analysis for Windows
- WinDump: the porting of
the famous tcpdump tool
- Analyzer: graphical network sniffer for Windows
- WebLibrary: a
simple tool used to create online documentation, that can be easily printed (maintaining a good looking layout) and includes PowerPoint slides to be used in class.
- 46Bouncer: a simple
tool that accepts IPv4/IPv6 connections and translates them to IPv6/IPv4.
Useful to make IPv4 servers / applications available on the IPv6 domain
- GT: a tool for extracting ground truth from traffic traces, developed in in collaboration with University of Brescia (Italy)
- iNFAnt: an engine for Non-Deterministic Automata on nVidia GPUs
Something about me
Born in Saluzzo (Cuneo, Italy), 15 november 1971. The same day Intel announced the 4004 chip.
BSc in Computer Engineering at Politecnico di Torino in July 1995.
PhD in Computer Engineering at Politecnico di Torino in January 2000.
Assistant Professor at Politecnico di Torino (Technical University of Torino), Visiting Faculty at Cisco Systems, San Jose, CA (USA). Responsible for the international students at the Department of Computer and Control Engineering.
Married with Daniela (2000), two kids: Francesco (2001) and Valentina (2006).
Interests: traveling, by plane and with my RV.