Office hours and appointments for students
I do not schedule fixed office hours. If you need an appointment, please check my calendar and follow the suggestions on that page.
I'm currently involved in investigating high-speed packet processing (i.e., 10Gbps and beyond), while maintaining flexibility. We designed several components that can be used to achieve this vision, from the highly successful NetPDL language, the NetVM virtual machine, and their integration in the NetBee library. I also tried to apply these technologies to the problem of Traffic Classification, hence I spent some time on that topic too. With some very smart PhD student we had a look at the word of network processors and multicore/graphical CPU for networking; the first result is the iNFAnt pattern matching engine on nVidia graphics cards.
For several years I've explored the world of network processing, a.k.a. how to make the network programmable. This concept is now the "Software Defined Networks" buzzword, although it is so vague that you can do almost everything under that umbrella. In any case, over the year, I moved away from simple network programmability and I started thinking about moving services (whatever services, starting with NFV) into the network. This is currently my main research activity, which oeriginated the FROG (Flexible and pROGrammable network device) open source project. Starting from 2017, we began to have fun with the eBPF technology, which enables lightweight network services that are executed directly in the LInux kernel. The (ongoing) result can be seen in the Polycube software framework.
My past research activities included Quality of Service in Packet Switched Networks, Scheduling Algorithms (particularly Class Based Queuing), Scheduling, Voice over IP, management of resources in peer-to-peer networks.
Some more pointers:
- Computer Networks Research Group (NetGroup)
- Proposals for MSc student theses
- My publications on the University institutional repository
Something about me
Born in Saluzzo (Cuneo, Italy), 15 november 1971. The same day Intel announced the 4004 chip.
BSc in Computer Engineering at Politecnico di Torino in July 1995.
PhD in Computer Engineering at Politecnico di Torino in January 2000.
Associate Professor at Politecnico di Torino (Technical University of Torino). Responsible for students and staff mobility with the Department of Computer and Control Engineering. Responsible for the Network and Multimedia Lab at Dept. of Control and Computer Engineering.
Married with Daniela (2000), one son (Francesco, 2001), one daughter (Valentina, 2006) and a little puppy, Whisky (2016).
Interests: history; travelling, particularly with my RV.